Many electronic devices include memory devices, e.g., Dynamic Random Access Memory (DRAM) devices, which are structured as a matrix of rows and columns Data is typically stored in such memory devices in a row, with current modern Double Data Rate (DDR) DRAM devices having up to 16K-bits in a row (i.e., a page). These electronic devices use these memory devices to construct physical memory space of the underlining computing system. In some instances a computing system may need to copy (or move) a block of memory within its memory space. A typical block size is the operating system page size which is typically at least 4 Kilo Bytes (KB). However, most DRAM devices used to implement the memory space are designed with relatively narrow (e.g., 4-bit, 8-bit, 16-bit) Input/Output (I/O) interfaces. Moreover the communication interface width between DRAM Dual In Line Memory Modules (DIMMs) (a group of DRAM devices) and processors is standardized and also narrow as well (64 bits). Thus, in existing architectures moving a large block of data (such as a page in the operating system) in physical memory space requires multiple cycles which step through sequential addresses in a row via the communication interface used to communicate with the external physical memory devices. Accordingly, efficient techniques to move data from one row to another within a memory device may find utility, e.g., in memory systems.